Open AccessTest Scheduling and Test Time Reduction for SoC by Using Enhanced Firefly Algorithm
Author(s) -
Gokul Chandrasekaran,
Gopinath Singaram,
Rajkumar Duraisamy,
Akash Sanjay Ghodake,
Parthiban Kunnathur Ganesan
Publication year - 2021
Publication title -
revue d'intelligence artificielle
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.146
H-Index - 14
eISSN - 1958-5748
pISSN - 0992-499X
DOI - 10.18280/ria.350310
Subject(s) - firefly algorithm , computer science , reduction (mathematics) , firefly protocol , algorithm , scheduling (production processes) , system on a chip , reliability engineering , real time computing , embedded system , engineering , mathematical optimization , mathematics , zoology , geometry , particle swarm optimization , biology
System-on-Chip (SoC) is an integration of electronic components and billions of transistors. Defects due to the base material is caused during the manufacturing of components. To overcome these issues testing of chips is necessary but total cost increases because of increasing test time. The main issues to be considered during testing of SoC are the time taken for testing and accessibility of core. Effective test scheduling should be done to minimize testing time. In this paper, an effective test scheduling mechanism to minimize testing time is proposed. The test time reduction causes test cost reduction. The Enhanced Firefly algorithm is used in this paper to minimize test time. Enhanced Firefly algorithm gives a better result than Ant colony and Firefly algorithms in terms of test time reduction thereby reduction test cost takes place.