Open AccessA Dual Frequency Compensation Technique to Improve Stability and Transient Response for a Three Stage Low-Drop-Out Linear Regulator
Author(s) -
Anass Slamti,
Youness Mehdaoui,
Driss Chenouni,
Zakia Lakhliai
Publication year - 2021
Publication title -
mathematical modelling and engineering problems/mathematical modelling of engineering problems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.26
H-Index - 11
eISSN - 2369-0747
pISSN - 2369-0739
DOI - 10.18280/mmep.080208
Subject(s) - low dropout regulator , dropout voltage , line regulation , voltage regulator , control theory (sociology) , transient response , frequency compensation , linear regulator , regulator , capacitor , voltage , load regulation , compensation (psychology) , transient (computer programming) , voltage divider , physics , engineering , electrical engineering , computer science , psychology , biochemistry , chemistry , control (management) , artificial intelligence , psychoanalysis , gene , operating system
A novel internal compensation technique named dual frequency compensation is proposed to improve the stability and the transient response of the on-chip output capacitor three stage low-drop-out linear voltage regulator (LDO). It exploits a combination of amplification and differentiation to sufficiently separate the dominant pole from the first non-dominant pole so that the latter is located after the unity gain frequency regardless of the load current value. The proposed LDO regulator is analyzed, designed, and simulated in standard 0.18 µm low voltage CMOS technology. The presented LDO regulator delivers a stable voltage of 1.2 V for an input supply voltage range of 1.35-1.85 V with a maximum line deviation of 4.68mV/V and can supply up to 150mA of the load current. The maximum transient variation of the output voltage is 54.5 mV when the load current pulses from 150mA to 0mA during a fall time of 1µs. The proposed LDO regulator has a low figure of merit compared with recent LDO regulators.