Open AccessAn Approach to the Construction of a Network Processing Unit
Author(s) -
Станислав Олегович Беззубцев,
Вячеслав Викторович Васин,
Дмитрий Юрьевич Волканов,
Шынар Рустембековна Жайлауова,
Владислав Александрович Мирошник,
Юлия Александровна Скобцова,
Руслан Леонидович Смелянский
Publication year - 2019
Publication title -
modelirovanie i analiz informacionnyh sistem
Language(s) - English
Resource type - Journals
eISSN - 2313-5417
pISSN - 1818-1015
DOI - 10.18255/1818-1015-2019-1-39-62
Subject(s) - computer science , pipeline (software) , network processor , openflow , computer architecture , systemc , packet processing , architecture , network architecture , embedded system , software , reference architecture , set (abstract data type) , throughput , microcontroller , network packet , software defined networking , software architecture , distributed computing , operating system , computer network , programming language , art , wireless , visual arts
The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.