Open AccessData Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs
Author(s) -
Сергеевна Комар
Publication year - 2017
Publication title -
modelirovanie i analiz informacionnyh sistem
Language(s) - English
Resource type - Journals
eISSN - 2313-5417
pISSN - 1818-1015
DOI - 10.18255/1818-1015-2017-4-434-444
Subject(s) - central processing unit , cpu shielding , computer science , cache , multi core processor , dependency (uml) , interface (matter) , parallel computing , embedded system , operating system , bubble , maximum bubble pressure method , software engineering