Open AccessDesign and Analysis of Low Power Dual Edge Triggered Mechanism Flip-Flop Employing Power Gating Methodology
Author(s) -
Prof. Virendra Umale
Publication year - 2020
Publication title -
international journal of new practices in management and engineering
Language(s) - English
Resource type - Journals
ISSN - 2250-0839
DOI - 10.17762/ijnpme.v6i01.53
Subject(s) - power gating , flip flop , power (physics) , transistor , gating , computer science , leakage power , power consumption , electronic engineering , circuit design , electrical engineering , enhanced data rates for gsm evolution , voltage , embedded system , engineering , telecommunications , physics , physiology , quantum mechanics , biology
The advancement of battery operated designs has abundantly increases the memory elements and registers to be operated in ultra-low power. That is the this paper we have proposed a design of CT_C DET flip-flop with power gating technique which is the most efficient power consuming reduction technique. The design of the power gating technique involves the pull-up transistor in the Vdd of the circuit and pull-down transistor in the ground terminal. This power gating technique reduces the power consumption by more than 40% than that of the existing design.