Open AccessDesign and analysis of Low Power High Speed Pulse Triggered Flip Flop
Author(s) -
Mr. Kankan Sarkar
Publication year - 2016
Publication title -
international journal of new practices in management and engineering
Language(s) - English
Resource type - Journals
ISSN - 2250-0839
DOI - 10.17762/ijnpme.v5i03.45
Subject(s) - flip flop , schematic , cadence , computer science , power consumption , power (physics) , pulse (music) , electronic engineering , critical path method , signal (programming language) , path (computing) , electrical engineering , detector , telecommunications , engineering , physics , enhanced data rates for gsm evolution , systems engineering , quantum mechanics , programming language
The main important aspect is to outline a high speed and utilization of low power pulse triggered flip-flop and simulate the same. Also, we have to minimize leakage in the consumption of power in a flip-flop by employing pulse triggering technique that is adopted for clocks. Here, to solve the problem in the discharging path of the similar flip flop implementations, we employ signal feed through technique. The discharge time is reduced by the proposed method. This design out performs all the other similar pulse triggered flip flop implementation both in speed and power consumption. Now, it is implemented by employing Cadence Virtuoso Schematic Composer in 90nm GPDK. Simulation is done by a simulator known as Spectre.