Open AccessLeakage Power Minimization Using Gating Technique In FPGA Controlled Device
Author(s) -
Mr. Sagar Kothawade
Publication year - 2013
Publication title -
international journal of new practices in management and engineering
Language(s) - English
Resource type - Journals
ISSN - 2250-0839
DOI - 10.17762/ijnpme.v2i04.22
Subject(s) - power gating , computer science , field programmable gate array , leakage (economics) , embedded system , leakage power , clock gating , asynchronous communication , power (physics) , reduction (mathematics) , power consumption , computer hardware , electronic engineering , electrical engineering , engineering , voltage , transistor , computer network , jitter , telecommunications , physics , quantum mechanics , clock signal , synchronous circuit , economics , macroeconomics , geometry , mathematics
FPGA based controlled devices are widely used in integrated chip sector provided the power consumed by such devices should be low. Leakage power takes vital part in contributing towards the total power consumption. This research work concentrates in proposing a power gating technique based on look up table approach. The novelty of this approach is that common look up tables are employed for asynchronous architectures for each leaf node. Due to this the leakage power and the total area overhead can be minimized. The proposed architecture is simulated through M-Power analysis and simulator tool for leaf nodes and efficiently utilizes H-tree methodology to minimize area. The reduction in number of look up tables leads to 45% to 50% reduction in leakage power of FPGA device.