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Power and Delay Analysis of Flip Flop Using Pulse Control Method
Author(s) -
Ms. Ritika Dhabliya
Publication year - 2013
Publication title -
international journal of new practices in management and engineering
Language(s) - English
Resource type - Journals
ISSN - 2250-0839
DOI - 10.17762/ijnpme.v2i03.19
Subject(s) - flip flop , power (physics) , computer science , pulse (music) , scheme (mathematics) , electronic engineering , transistor , energy (signal processing) , power control , pulse width modulation , control (management) , electrical engineering , control theory (sociology) , engineering , cmos , mathematics , telecommunications , voltage , physics , artificial intelligence , statistics , mathematical analysis , quantum mechanics , detector
The past few years, increasing difficulty in integration can be solved by low power, which is very important and also choosing flip-flop solves the challenges like low power. In this paper, we design and compare the power problem of various indirect pulse triggered flip flop are examined. It can be attained by reconstructing the lower part of Single-ended Conditional Capture Energy Recovery (SCCER) design and by employing the control pulse scheme. The results after the simulation derives transistor count and power required are significantly reduced in the proposed design over existing design.

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