Open AccessFPGA Implementation of Hardware Architecture for H264/AV Codec Standards
Author(s) -
Prof. Naveen Jain
Publication year - 2013
Publication title -
international journal of new practices in management and engineering
Language(s) - English
Resource type - Journals
ISSN - 2250-0839
DOI - 10.17762/ijnpme.v2i01.11
Subject(s) - computer science , codec , discrete cosine transform , stratix , encoder , field programmable gate array , computer hardware , embedded system , virtex , data compression , transform coding , computer architecture , artificial intelligence , image (mathematics) , operating system
The proposed work is a modern hardware based architecture for performing transformation, quantisation and prediction is designed which is used for H.264/AVC video standards. This designed hardware find its importance in advanced H264 encoders which are repeatedly find its application in HDTV applications. The H264/AV Codec does video compression and video decompression for prospect broadband and wireless networks. A low complexity discrete cosine transform is used by DSP embedded multiplier. An intra-prediction equation are employed to get low latency, high throughput, efficient utilization of resources. The proposed architecture also employs both pipeline & parallel process methods. The proposed architecture is implemented using VHDL and synthesised for Virtex 5, and the device is 5vlx50tff665.