Open AccessVedic Multiplier Implementation for High Speed Factorial Computation
Author(s) -
Prof. Sharayu Waghmare
Publication year - 2012
Publication title -
international journal of new practices in management and engineering
Language(s) - English
Resource type - Journals
ISSN - 2250-0839
DOI - 10.17762/ijnpme.v1i04.8
Subject(s) - multiplier (economics) , factorial , computation , arithmetic , factorial experiment , very large scale integration , computer science , architecture , mathematics , parallel computing , algorithm , statistics , embedded system , art , mathematical analysis , economics , visual arts , macroeconomics
Vedic Mathematics arise from the prehistoric classification of Indian mathematics that was recreated by Tirthaji. Ancient mathematical operations are depending on sixteen methods. In this article, a new VLSI architecture to compute factorial of the given number with Vedic based multiplier is proposed. Simulations are performed using Xilinx ISE 14.2. Effective comparative analysis is made with existing multipliers to prove the momentous development in competence and high speed operation. This efficient multiplier is implemented in the proposed factorial architecture which significantly reduces the path delay and provides better optimization.