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Design of Low Power SRAM using Hierarchical Divided Bit-line Approach in 180-nm Technology
Author(s) -
Mohammed Sayeeduddin Habeeb,
Mohd Salahuddin
Publication year - 2016
Publication title -
international journal of engineering research and technology
Language(s) - English
Resource type - Journals
ISSN - 2278-0181
DOI - 10.17577/ijertv5is020152
Subject(s) - bit (key) , static random access memory , line (geometry) , power (physics) , computer science , electronic engineering , electrical engineering , mathematics , engineering , computer hardware , physics , computer network , geometry , quantum mechanics

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