Open AccessDual Recycled Charge Power Gating For Retaining Data and Saving Leakage
Author(s) -
Huan Minh Vo,
Quoc Ai Dao,
Vietnam Education
Publication year - 2018
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2018/v11i6/117898
Subject(s) - power gating , sleep mode , adder , computer science , nmos logic , clock gating , electronic circuit , leakage (economics) , pmos logic , electronic engineering , standby power , electrical engineering , power (physics) , transistor , voltage , engineering , power consumption , cmos , physics , quantum mechanics , clock signal , synchronous circuit , economics , macroeconomics