Open AccessDesign and Implementation of FPGA based 64-bit MAC Unit using VEDIC Multiplier and Reversible Logic Gates
Author(s) -
P. SivaNagendra Reddy,
M. Saraswathi
Publication year - 2017
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2017/v10i3/109413
Subject(s) - multiplier (economics) , adder , computer science , verilog , arithmetic , field programmable gate array , logic gate , computer hardware , mathematics , algorithm , telecommunications , economics , macroeconomics , latency (audio)