Open AccessBCD Adder Design using New Reversible Logic for Low Power Applications
Author(s) -
S. Uma,
M. Parvathi
Publication year - 2017
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2017/v10i19/115514
Subject(s) - adder , computer science , arithmetic , power (physics) , telecommunications , mathematics , latency (audio) , physics , quantum mechanics