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Efficient Modified Booth Multiplier for Signal Processing Applications
Author(s) -
S. Tamilselvan,
P. Nithya
Publication year - 2017
Publication title -
indian journal of science and technology
Language(s) - Uncategorized
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2017/v10i14/107622
Subject(s) - computer science , multiplier (economics) , booth's multiplication algorithm , signal processing , arithmetic , digital signal processing , computer hardware , mathematics , telecommunications , adder , latency (audio) , economics , macroeconomics

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