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Register Embedded Self Immunity using Reversible Logic Gates
Author(s) -
Suresh Reddy Velagala,
M. V. Nageswara Rao
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - Uncategorized
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9is1/107918
Subject(s) - register file , computer science , soft error , reliability (semiconductor) , logic gate , error detection and correction , code (set theory) , computer hardware , arithmetic , power (physics) , embedded system , algorithm , electronic engineering , mathematics , engineering , physics , instruction set , programming language , set (abstract data type) , quantum mechanics

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