
FPGA Implementation of Convolution for Data Hiding Application
Author(s) -
B. Devi Vara Prasad,
N. V. Lalitha,
G. Suresh
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9is1/107890
Subject(s) - multiplier (economics) , booth's multiplication algorithm , convolution (computer science) , field programmable gate array , computer science , power consumption , deconvolution , arithmetic , digital signal processing , adder , mathematics , algorithm , computer hardware , power (physics) , artificial intelligence , telecommunications , physics , quantum mechanics , artificial neural network , economics , macroeconomics , latency (audio)