Open AccessFPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes
Author(s) -
Sandeep Kakde,
Atish Khobragade,
M. D. Ekbal Husain
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i48/97269
Subject(s) - low density parity check code , computer science , field programmable gate array , soft decision decoder , decoding methods , parallel computing , very large scale integration , throughput , concatenated error correction code , serial concatenated convolutional codes , turbo code , sequential decoding , algorithm , parity check matrix , block code , computer hardware , embedded system , telecommunications , wireless