Open AccessA Novel High Speed Simulated Annealing Algorithm for Non-Slicing VLSI Floorplanning using B*-Tree Representation
Author(s) -
Raj C. Shah,
Manu Bansal
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i48/94334
Subject(s) - floorplan , very large scale integration , computer science , simulated annealing , parallel computing , algorithm , physical design , chip , sizing , circuit design , embedded system , art , telecommunications , visual arts