Open AccessHigh Performance FIFO Design for Processor through Voltage Scaling Technique
Author(s) -
Abhay Saxena,
Ashutosh Kumar Bhatt,
Parth Gautam,
Puneet Verma,
Chandrashekhar Patel
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i46/106916
Subject(s) - frequency scaling , fifo (computing and electronics) , computer science , field programmable gate array , scaling , voltage , power consumption , power (physics) , energy consumption , embedded system , computer hardware , electrical engineering , engineering , physics , geometry , mathematics , quantum mechanics