Open AccessDesign and Implementation of Floating Point Unit using 15 nm FIFET
Author(s) -
R. Dhanabal,
Sarat Kumar Sahoo
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i37/102131
Subject(s) - computer science , adder , comparator , computer hardware , multiplier (economics) , ieee floating point , 4 bit , floating point , arithmetic , 16 bit , transistor count , transistor , cmos , electronic engineering , electrical engineering , mathematics , latency (audio) , algorithm , engineering , voltage , telecommunications , economics , macroeconomics