Open AccessTiming Aware IR Drop Analysis in Microprocessor without Interlocked Pipelined Stage (MIPS) Design using Power/Ground Padding
Author(s) -
S. Malarvizhi,
Rakshaka Ramu,
J. Manjula
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i36/94586
Subject(s) - computer science , cadence , microprocessor , skew , physical design , power network design , floor plan , signal integrity , rdm , drop (telecommunication) , embedded system , computer hardware , circuit design , chip , electronic engineering , computer network , telecommunications , interconnection , archaeology , engineering , history