Open AccessPhysical Design Implementation of 16 Bit Risc Processor
Author(s) -
Devaraconda Dinesh,
Ramesh Kumar
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i36/102911
Subject(s) - computer science , routing (electronic design automation) , verilog , process (computing) , embedded system , state (computer science) , placement , reduced instruction set computing , physical design , idle , computer hardware , instruction set , field programmable gate array , operating system , circuit design , programming language