Open AccessRegister Free Polar Codes Based Partially Parallel Encoder and Decoder Architecture
Author(s) -
K. Saranya Devi,
R. Muthaiah
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i29/93498
Subject(s) - computer science , encoder , parallel computing , shift register , computer hardware , decoding methods , multiplexer , encoding (memory) , transmission (telecommunications) , algorithm , multiplexing , telecommunications , chip , operating system , artificial intelligence