Open AccessLow Latency Noc with Dynamic Priority based Matrix Arbiter
Author(s) -
J. Arjana
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i29/91707
Subject(s) - arbiter , computer science , router , network on a chip , network packet , one armed router , latency (audio) , core router , computer network , scheduling (production processes) , arbitration , parallel computing , embedded system , distributed computing , telecommunications , operations management , economics , political science , law