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Hybrid Integration in 3D NoC with Efficient Path Establishment Mechanism in Circuit Switching
Author(s) -
S Aishwarya,
D. Muralidharan
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i29/91705
Subject(s) - computer science , circuit switching , scalability , network on a chip , network topology , latency (audio) , network packet , quality of service , computer network , interconnection , embedded system , topology (electrical circuits) , telecommunications , electrical engineering , engineering , database

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