Open AccessA VLSI Architecture of Root Raised Cosine Filter Using Efficient Algorithm
Author(s) -
N. Nivedha,
R. Muthaiah
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i29/90908
Subject(s) - adder , algorithm , computer science , multiplexer , multiplication (music) , booth's multiplication algorithm , multiplier (economics) , reduction (mathematics) , very large scale integration , arithmetic , filter (signal processing) , computer hardware , parallel computing , mathematics , embedded system , multiplexing , telecommunications , geometry , combinatorics , economics , computer vision , macroeconomics , latency (audio)