Open AccessA Hybrid Topology for Frequency Divider using PLL Application
Author(s) -
Adhithan Pon,
R. Parameshwaran
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i29/90795
Subject(s) - frequency divider , topology (electrical circuits) , nand gate , computer science , transistor , phase locked loop , current divider , power (physics) , cmos , electrical engineering , electronic engineering , logic gate , engineering , physics , phase noise , voltage , quantum mechanics