Open AccessBuilt in Self Test Architecture using Concurrent Approach
Author(s) -
M. Dodiya Chandni,
V. Ravi
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9i20/89762
Subject(s) - computer science , built in self test , shift register , latency (audio) , test compression , automatic test pattern generation , arithmetic logic unit , parallel computing , overhead (engineering) , computer hardware , cellular automaton , fault coverage , combinational logic , algorithm , arithmetic , embedded system , electronic circuit , logic gate , mathematics , chip , telecommunications , electrical engineering , engineering , operating system