Open AccessLow Power Estimation on Test Compression Technique for SoC based Design
Author(s) -
P. Raja Gopal,
S. Saravanan
Publication year - 2015
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2015/v8i14/61848
Subject(s) - benchmark (surveying) , power (physics) , test compression , computer science , system on a chip , dissipation , chip , metric (unit) , power consumption , very large scale integration , reduction (mathematics) , test data , electronic circuit , embedded system , algorithm , mathematics , automatic test pattern generation , electrical engineering , engineering , telecommunications , operations management , physics , geometry , geodesy , quantum mechanics , thermodynamics , geography , programming language