Open AccessReconfigurable Adaptive Routing Buffer Design for Scalable Power Efficient Network On Chip
Author(s) -
G. Selvaraj,
K. R. Kashwan
Publication year - 2015
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2015/v8i12/59145
Subject(s) - computer science , network on a chip , embedded system , scalability , chip , system on a chip , routing (electronic design automation) , very large scale integration , reduction (mathematics) , power network design , computer architecture , telecommunications , geometry , mathematics , database