Open AccessFPGA and ASIC Implementation of Systolic Arrays for the Design of Optimized Median Filter in Digital Image Processing Applications
Author(s) -
Kalyan Sagar Kadali
Publication year - 2014
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2014/v7sp7.20
Subject(s) - field programmable gate array , application specific integrated circuit , computer science , systolic array , median filter , digital image processing , filter (signal processing) , image processing , digital filter , computer hardware , image (mathematics) , computer vision , embedded system , very large scale integration
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