Open AccessDesign and Implementation of Dual Core and Quad Core Processor in Vertex 6 FPGA Using Pipelined RISC Architecture
Author(s) -
Mr. Rakesh M R
Publication year - 2018
Publication title -
ijireeice
Language(s) - English
Resource type - Journals
eISSN - 2321-5526
pISSN - 2321-2004
DOI - 10.17148/ijireeice.2018.6114
Subject(s) - field programmable gate array , computer science , computer architecture , architecture , core (optical fiber) , parallel computing , multi core processor , dual (grammatical number) , reduced instruction set computing , embedded system , microarchitecture , many core , vertex (graph theory) , instruction set , graph , theoretical computer science , art , telecommunications , literature , visual arts
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