Open AccessA Novel VLSI Design of Hybrid Carry Skip Adder Implementation based on Verilog HDL
Author(s) -
C. Banupriya,
S. Sridevi Sathya Priya
Publication year - 2017
Publication title -
international journal of innovative research in electrical, electronics, instrumentation and control engineering
Language(s) - English
Resource type - Journals
eISSN - 2321-5526
pISSN - 2321-2004
DOI - 10.17148/ijireeice.2017.5642
Subject(s) - verilog , adder , very large scale integration , carry (investment) , computer science , computer architecture , carry save adder , parallel computing , embedded system , arithmetic , computer hardware , field programmable gate array , mathematics , latency (audio) , telecommunications , finance , economics