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Design of Low-Power Reversible Carry Select Adder using D-Latch
Author(s) -
Chaluvadi Prasanth,
Mante Anil,
Kolla Sahithi,
Kotagaram Raviteja
Publication year - 2017
Publication title -
ijireeice
Language(s) - English
Resource type - Journals
eISSN - 2321-5526
pISSN - 2321-2004
DOI - 10.17148/ijireeice.2017.5410
Subject(s) - adder , carry (investment) , power (physics) , carry save adder , serial binary adder , computer science , arithmetic , electrical engineering , mathematics , engineering , physics , telecommunications , business , thermodynamics , finance , latency (audio)

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