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VHDL implementation of AES-128 on FPGA
Author(s) -
NITIN R. CHAVAN,
Suresh A. Annadate
Publication year - 2015
Publication title -
ijireeice
Language(s) - English
Resource type - Journals
eISSN - 2321-5526
pISSN - 2321-2004
DOI - 10.17148/ijireeice.2015.3108
Subject(s) - vhdl , field programmable gate array , computer science , embedded system , computer architecture , computer hardware , parallel computing

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