Open AccessA 16X16 High Speed Vedic Multiplier for Area and Power Reduction
Author(s) -
Muruganantham Mr.T.,
N. Nagarajan,
Syed Husain Mr.S.
Publication year - 2019
Publication title -
international journal of advanced research in computer and communication engineering
Language(s) - English
Resource type - Journals
eISSN - 2319-5940
pISSN - 2278-1021
DOI - 10.17148/ijarcce.2019.8609
Subject(s) - multiplier (economics) , reduction (mathematics) , arithmetic , mathematics , computer science , economics , geometry , keynesian economics