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Design of Reversible Excess-3 Adder and Subtractor
Author(s) -
Pujitha Chaluvadi,
Mahi Pranay,
P Sukesh,
Kuruva Madhu
Publication year - 2017
Publication title -
ijarcce
Language(s) - English
Resource type - Journals
eISSN - 2319-5940
pISSN - 2278-1021
DOI - 10.17148/ijarcce.2017.63142
Subject(s) - adder , subtractor , arithmetic , carry save adder , computer science , parallel computing , mathematics , telecommunications , latency (audio)

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