Open AccessAn Efficient NAND Gate Based Glitch-free All-Digital Duty-Cycle Corrector Architecture
Author(s) -
S. Theivanayaki,
M. Sathiskumar
Publication year - 2015
Publication title -
ijarcce
Language(s) - Uncategorized
Resource type - Journals
eISSN - 2319-5940
pISSN - 2278-1021
DOI - 10.17148/ijarcce.2015.4390
Subject(s) - glitch , nand gate , duty cycle , computer science , architecture , logic gate , electrical engineering , engineering , telecommunications , algorithm , geography , voltage , archaeology , detector
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