Open AccessSimulation of a tripled majority voter by Quartus Prime State Machine
Author(s) -
Artem V. Grekov,
AUTHOR_ID
Publication year - 2021
Publication title -
vestnik permskogo universiteta. matematika, mehanika, informatika
Language(s) - English
Resource type - Journals
ISSN - 1993-0550
DOI - 10.17072/1993-0550-2021-1-57-60
Subject(s) - automaton , field programmable gate array , prime (order theory) , computer science , finite state machine , graph , cellular automaton , state (computer science) , adder , theoretical computer science , parallel computing , algorithm , mathematics , embedded system , combinatorics , telecommunications , latency (audio)
A triple majority element based on a full adder in the Quartus Prime State Machine is investigated to create highly reliable FPGA-based digital automata. For this purpose, two new groups of inputs are added to the previously developed automaton graph. Modeling the failure of one of the three majorities is performed by specifying the corresponding constant in one of the three input groups. The performance indicators of the developed device are evaluated.