Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework
Author(s) -
Yukihide Kohira,
Tani Shuhei,
Atsushi Takahashi
Publication year - 2009
Publication title -
ieice transactions on fundamentals of electronics communications and computer sciences
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.188
H-Index - 52
eISSN - 1745-1337
pISSN - 0916-8508
DOI - 10.1587/transfun.e92.a.1106
Subject(s) - synchronous circuit , computer science , schedule , clock skew , minification , timing failure , digital clock manager , clock domain crossing , clock gating , clock signal , real time computing , control theory (sociology) , telecommunications , jitter , control (management) , artificial intelligence , programming language , operating system
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