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Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism
Author(s) -
Yuta Ukon,
Shimpei Sato,
Atsushi Takahashi
Publication year - 2020
Publication title -
ieice transactions on electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.182
H-Index - 48
eISSN - 1745-1353
pISSN - 0916-8524
DOI - 10.1587/transele.2020cdp0007
Subject(s) - computer science , adder , image processing , word error rate , electronic circuit , computer hardware , electronic engineering , latency (audio) , artificial intelligence , image (mathematics) , electrical engineering , engineering , telecommunications

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