Open AccessCertifying Loop Pipelining Transformations in Behavioral Synthesis
Author(s) -
Disha Puri
Publication year - 2000
Language(s) - Uncategorized
Resource type - Reports
DOI - 10.15760/etd.5364
Subject(s) - computer science , verilog , systemc , hardware description language , vhdl , abstraction , correctness , high level synthesis , programming language , process (computing) , control flow , computer architecture , design flow , embedded system , field programmable gate array , philosophy , epistemology
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