Open AccessDesign and Implementation of High Speed 8-Bit Vedic Multiplier on FPGA
Author(s) -
B.Madhu Latha,
Bhukya Nageswar Rao
Publication year - 2014
Publication title -
international journal of advanced research in electrical, electronics and instrumentation engineering
Language(s) - English
Resource type - Journals
eISSN - 2320-3765
pISSN - 2278-8875
DOI - 10.15662/ijareeie.2014.0308087
Subject(s) - multiplier (economics) , field programmable gate array , arithmetic , bit (key) , computer science , computer hardware , parallel computing , computer architecture , mathematics , computer security , keynesian economics , economics