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An Efficient Implementation of Double Precision Floating Point Multiplier Using Booth Algorithm
Author(s) -
Pallavi Ramteke,
DR. N. N. MHALA,
PROF. P. R. LAKHE
Publication year - 2014
Publication title -
international journal of advanced research in electrical, electronics and instrumentation engineering
Language(s) - English
Resource type - Journals
eISSN - 2320-3765
pISSN - 2278-8875
DOI - 10.15662/ijareeie.2014.0307018
Subject(s) - computer science , algorithm , multiplier (economics) , double precision floating point format , floating point , booth's multiplication algorithm , arithmetic , mathematics , telecommunications , adder , economics , macroeconomics , latency (audio)

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