Open AccessFPGA IMPLEMENTATION OF 4-BIT PARALLEL CYCLIC REDUNDANCY CODE
Author(s) -
Hemant Sharma,
Samyak Tomar,
Jitendra Kanungo
Publication year - 2015
Publication title -
international journal of research in engineering and technology
Language(s) - Uncategorized
Resource type - Journals
eISSN - 2321-7308
pISSN - 2319-1163
DOI - 10.15623/ijret.2015.0411021
Subject(s) - field programmable gate array , computer science , redundancy (engineering) , cyclic redundancy check , parallel computing , code (set theory) , bit (key) , computer hardware , embedded system , arithmetic , algorithm , programming language , mathematics , operating system , computer network , decoding methods , set (abstract data type)