Open AccessDESIGN AND VERIFICATION OF PIPELINED PARALLEL ARCHITECTURE IMPLEMENTATION IN FPGA FOR BIT ERROR RATE TESTER
Author(s) -
. T.Anbuselvi
Publication year - 2014
Publication title -
international journal of research in engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 2321-7308
pISSN - 2319-1163
DOI - 10.15623/ijret.2014.0314006
Subject(s) - field programmable gate array , computer science , embedded system , architecture , bit (key) , computer hardware , computer architecture , computer network , art , visual arts