Open AccessDESIGN OF LOW POWER 4-BIT FULL ADDER USING SLEEPY KEEPER APPROACH
Author(s) -
B. Srujana Sri,
B. Saraswathi,
G. Arun Kumar,
Arjun Singh
Publication year - 2012
Publication title -
international journal of research in engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 2321-7308
pISSN - 2319-1163
DOI - 10.15623/ijret.2012.0103028
Subject(s) - adder , bit (key) , power (physics) , arithmetic , 16 bit , computer science , electronic engineering , electrical engineering , computer hardware , engineering , telecommunications , mathematics , physics , computer network , quantum mechanics , latency (audio)