
Design of an Efficient Parallel Comparator Architecture for Low Power Delay Product
Author(s) -
Mangal Deep Gupta,
R. K. Chauhan
Publication year - 2021
Publication title -
advances in electrical and electronic engineering/advances in electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.225
H-Index - 19
eISSN - 1804-3119
pISSN - 1336-1376
DOI - 10.15598/aeee.v19i2.4101
Subject(s) - comparator , power–delay product , power (physics) , product (mathematics) , architecture , computer science , parallel architecture , parallel computing , computer architecture , electrical engineering , electronic engineering , mathematics , engineering , telecommunications , physics , voltage , art , adder , geometry , quantum mechanics , visual arts , latency (audio)