
FPGA LUT with two Shannon decompozition outputs
Author(s) -
Sergey F. Tyurin,
Maksim A. Chudinov
Publication year - 2019
Publication title -
vestnik permskogo nacionalʹnogo issledovatelʹskogo politehničeskogo universiteta. èlektrotehnika, informacionnye tehnologii, sistemy upravleniâ
Language(s) - English
Resource type - Journals
eISSN - 2305-2767
pISSN - 2224-9397
DOI - 10.15593/2224-9397/2019.1.09
Subject(s) - lookup table , field programmable gate array , computer science , parallel computing , arithmetic , computer hardware , computer architecture , mathematics , operating system